The present invention relates to the fabrication of semiconductor device interconnect lines and via plugs which are fabricated using dual damascene techniques.
A semiconductor device such as an IC (integrated circuit) generally has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Advances in semiconductor materials and processing techniques have resulted in reducing the overall size of the IC while increasing the number of circuit elements. Additional miniaturization is highly desirable for improved IC performance and cost reduction. Interconnects provide the electrical connections between the various electronic elements of an IC and they form the connections between these elements and the device""s external contact elements, such as pins, for connecting the IC to other circuits. Typically, interconnect lines form the horizontal connections between the electronic circuit elements while conductive via plugs form the vertical connections between the electronic circuit elements, resulting in layered connections.
A variety of techniques are employed to create interconnect lines and vias. One such technique involves a process generally referred to as dual damascene, which includes forming a trench and an underlying via hole. The trench and the via hole are simultaneous filled with a conductor material, for example a metal, thus simultaneously forming an interconnect line and an underlying via plug. Examples of conventional dual damascene fabrication techniques are disclosed in Kaanta et al., xe2x80x9cDual Damascene: A ULSI Wiring Technologyxe2x80x9d, Jun. 11-12, 1991, VMIC Conference, IEEE, pages 144-152 and in U.S. Pat. No. 5,635,423 to Huang et al., 1997.
The prior art techniques, such as those disclosed in the above referenced publications, rely on forming the trench and the via hole for the dual damascene structure in the same etching step shown in FIGS. 1A-ID. As depicted in FIG. 1A, a first dielectric layer 110 is deposited on a semiconductor substrate 112. An etch stop layer 116, such as silicon nitride, is deposited on first dielectric layer 110. A second dielectric layer 118 is deposited on etch stop 116, and an etch mask 120 is positioned on dielectric layer 118. Etch mask 120 is patterned (121) for etching a via hole, having a width W1. Second dielectric layer 118 is etched using a first anisotropic etch procedure to form a hole 122 (FIG. 1A) conforming to the via pattern. This etching procedure is stopped at etch stop layer 116. Etch mask 120 is removed and another etch mask 124 (see, FIG. 1B) is positioned on second dielectric layer 118 such that it is patterned (126) for forming a trench which is intended to include the previously formed hole 122 conforming to the via pattern. However, when the trench pattern is misaligned with hole 122 (see, FIG. 1B), portion 123 of hole 122 is covered by mask 124. As shown in phantom, a second anisotropic etch procedure is used to etch the trench pattern through second dielectric layer 118. Simultaneously, hole 122 is extended to substrate 112, by etching through etch stop layer 116 and through first dielectric layer 110. In this dual damascene technique the first etch procedure has a greater selectivity to etch stop layer 116 than the second etch procedure.
As shown in FIG. 1C, the second etch procedure results in forming trench 128 and via hole 130 which extends to semiconductor substrate 112. It will be noted that portion 123 of trench 128 is a widened portion of the trench due to the misalignment between via pattern 121 and trench pattern 126. However the widened portion 123 is not contiguous with underlying via hole 130, thereby reducing via pattern width W1 (FIG. 1A) to via hole width W2 (FIG. 1C). In other words, the width of the via hole is smaller than the width of the via pattern as a result of the misalignment. This prior art technique has other shortcomings as well, e.g. undeveloped resist (not shown) remaining on the bottom of hole 122, thereby impeding the complete etching of hole 130, and attack on the etch stop during via etch. Also, this procedure requires an etch chemistry which is very selective with respect to photoresist materials, which is difficult to achieve with dielectrics such as those having a low dielectric constant.
Mask 124 is removed, after which trench 128 and via hole 130 are simultaneously filled with a suitable conductive metal 132 (see, FIG. 1D) forming metallized line 134 and via plug 136 which contacts substrate 112. Excess metal 132 is removed from the surface of layer 118, for example by planarizing, to define line 134. Dual damascene line 134 has a widened section 138 resulting from the via misalignment, but this widened section is not contiguous with via plug 136, thus resulting in a reduced plug width as compared with the width of the via pattern.
Prior art techniques for forming via holes and trenches suitable for dual damascene fabrication result in a reduced via width when the trench pattern and the via pattern are misaligned, as described above in connection with FIGS. 1A-1D, particularly when the trench pattern width is substantially the same as the via pattern width. A significant reduction in via width makes it more difficult to fill the via hole with conductive metal, particularly when the via hole has a relatively high aspect ratio. Filling difficulties can result in filling the via incompletely, causing electrical or mechanical failure of the dual damascene structure. Also, a reduced width of the via results in a reduced contact area between the interconnect line and the underlying via plug, which can cause a highly disadvantageous increase in the contact resistance between the line and the via plug. Also, the prior art techniques described in connection with FIGS. 1A-1D result in widening the line at the misalignment point. Widening a line can result in an electrical short between closely spaced adjacent lines.
Accordingly, the need exists for improved methods for dual damascene fabrication to compensate for misalignment between the via mask and the trench mask and to overcome fabrication problems resulting from the presence of undeveloped resist impeding the complete formation of via holes as well as the need for etch chemistry which is very selective with respect to photoresist and etch stop layers.
The present invention provides novel methods and structures for dual damascene integrated circuit devices which overcome the prior art shortcomings described above.
In one embodiment of the present invention a first dielectric layer is deposited on a substrate, such as a semiconductor substrate. This is followed by the deposition of an etch stop layer upon which a second dielectric layer is deposited. The first and second dielectric layers have similar etching characteristics, i.e. the etching properties of these layers are such that the layers are capable of being etched at similar etching rates in a particular etch chemistry. A hard mask layer is deposited on the second dielectric layer. This hard mask has similar etching characteristics as the etch stop layer. A photoresist having a trench pattern is deposited on the hard mask layer. The trench pattern is transferred to the hard mask, after which this resist is stripped. A photoresist is then deposited on the hard mask, and a via pattern is developed in the photoresist over the underlying trench pattern in the hard mask. The via pattern is anisotropically etched through any portions of the hard mask which protrude into the via pattern due to a misalignment between the via pattern and the trench pattern. The via pattern is then anisotropically etched through the second dielectric layer and through the etch stop layer. After removal of the resist, a subsequent anisotropic procedure is used to simultaneously transfer the trench pattern through the second dielectric layer and to transfer the via pattern through the first dielectric layer. A further anisotropic etching procedure is used to simultaneously etch the trench pattern through the etch stop layer and to remove the hard mask layer, thus forming a via hole and a trench. This novel technique results in the formation of a misalignment compensating portion which is contiguous with the trench and the via hole such that there is no reduction in the width of the via hole when the via mask and the trench mask are misaligned. A dual damascene structure is fabricated by simultaneously filling the via hole and the trench with a conductive material such as a metal. This structure includes a misalignment compensating segment which is contiguous with the dual damascene line and the corresponding via plug, such that the width of the via plug is not reduced when the via mask and the trench mask are misaligned. The misalignment compensating feature of this embodiment causes the trench and the line to be widened at the misalignment compensating segment.
In an alternate embodiment of the above described invention, an additional hard mask layer such as a nitride is deposited on the above described hard mask layer when the latter mask comprises an oxide which is deposited on a second dielectric layer comprising a material having a low ( less than 3.5) dielectric constant. A photoresist having a trench pattern is provided on the nitride mask. The mask pattern is transferred to the nitride mask after which the resist is stripped. The trench mask is then transferred to the oxide mask, and the nitride mask is removed. The techniques of the present invention are then utilized as described above in order to fabricate the dual damascene structures. This alternate embodiment is particularly advantageous when the processing techniques for stripping resist affect the second dielectric layer.
In another embodiment of the present invention a first dielectric layer is deposited on a substrate, such as a semiconductor substrate, followed by the deposition of an etch stop layer. A second dielectric layer is deposited on the etch stop layer. The first and second dielectric layers have similar etching characteristics. A hard mask layer having similar etching characteristics as the etch stop layer is deposited on the second dielectric layer. A photoresist having a via pattern is provided on the hard mask layer. This via pattern is transferred to the hard mask layer after which the photoresist is removed. A photoresist is then deposited on the hard mask layer and a trench pattern is developed in this photoresist over the underlying via pattern. The via pattern which is located in the photoresist trench pattern is anisotropically etched through the second dielectric layer. An additional anisotropic etching procedure is used to etch the trench pattern through the hard mask layer and to simultaneously etch the via pattern through the etch stop layer. The trench pattern and the via pattern are then anisotropically simultaneously etched through the second and first dielectric layers respectively. The photoresist and the hard mask are removed, resulting in the formation of a trench and a via hole. The trench width of this embodiment conforms to the trench pattern even when the via pattern and the mask pattern are misaligned. However, misalignment causes a reduction in the via width when the trench pattern width and the via pattern width are similar. A dual damascene structure is formed by simultaneously filling the via hole and the trench with a suitable conductive material, such as a metal, wherein misalignment causes a reduction in the width of the via plug because the via width is determined by the width of the trench mask. Misalignment does not cause the line to be widened thus eliminating the problem of electrical shorts between closely spaced interconnect lines.
In yet another embodiment of the present invention, single layer etch masks are utilized wherein a silicon-based photosensitive material forms a hard mask upon exposure to radiation. Suitable examples of these mask materials include plasma polymerized methylsilane which is converted to plasma polymerized methylsilane oxide when exposed to UV light, thus forming a hard mask. These masks are utilized in combination with the above described embodiments of the invention.
In additional embodiments of the present invention, manufacturing systems are provided for forming fabricated structures, such as the IC structures of the present invention. These systems include a controller, such as a computer, which is adapted for interacting with a plurality of fabrication stations. Each of these fabrication stations performs a processing step which is utilized to fabricate the IC structures. Operative links provide connections between the controller and the manufacturing stations. A data structure, such as a computer program, causes the controller to control the processing steps which are performed at the fabrication stations. Preferably, the data structure is provided on a removable electronic storage medium.
The embodiments of the present invention result in reduced etching degradation of etch stop and photoresist layers because the trench and the via hole are formed simultaneously.